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| author | Felix Singer <felixsinger@posteo.net> | 2020-12-07 01:28:59 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-08 21:16:30 +0000 |
| commit | 1e3b2ce061626e6c5a7d7f89d40a854bac16f3d4 (patch) | |
| tree | b4c9e92a814f0cb0d75233d5d1526fbb707a6e8e /src/mainboard/google/sarien | |
| parent | 77562cf95e8b5911919fc346949bc17eb32d8b87 (diff) | |
| download | coreboot-1e3b2ce061626e6c5a7d7f89d40a854bac16f3d4.tar.xz | |
soc/intel/cannonlake: Align SATA mode names with soc/skl
Align the SATA mode names with soc/skl providing a consistent API.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/google/sarien')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 9e05213440..69e4e7d059 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 005a783e4f..021feba777 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" |