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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2019-01-14 17:56:51 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-01-18 08:15:58 +0000
commit2dfa53f80ecfbfe7e407a44af20a562f35faedd8 (patch)
treef2786c7093924a32147dad3308bcc37e9c31c973 /src/mainboard/google/sarien
parent72812fa51671a616d466499f0aa15cae121f1ae5 (diff)
downloadcoreboot-2dfa53f80ecfbfe7e407a44af20a562f35faedd8.tar.xz
mb/google/sarien/variants: Add Thermal Sensors information
Add available thermal sensors information for CPU throttling action. BRANCH=None BUG=b:120058043 TEST=Built and tested on Arcada system Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/sarien')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl22
-rw-r--r--src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl22
2 files changed, 36 insertions, 8 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
index ff59e3ce72..fcc87988da 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
@@ -16,16 +16,24 @@
#define DPTF_CPU_PASSIVE 80
#define DPTF_CPU_CRITICAL 100
+/* Skin Sensor for CPU VR temperature monitor */
#define DPTF_TSR0_SENSOR_ID 1
-#define DPTF_TSR0_SENSOR_NAME "Thermal 1"
+#define DPTF_TSR0_SENSOR_NAME "Skin"
#define DPTF_TSR0_PASSIVE 55
-#define DPTF_TSR0_CRITICAL 80
+#define DPTF_TSR0_CRITICAL 70
+/* Memory Sensor for DDR temperature monitor */
#define DPTF_TSR1_SENSOR_ID 2
-#define DPTF_TSR1_SENSOR_NAME "Thermal 2"
+#define DPTF_TSR1_SENSOR_NAME "DDR"
#define DPTF_TSR1_PASSIVE 55
#define DPTF_TSR1_CRITICAL 80
+/* M.2 Sensor for Ambient temperature monitor */
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "Ambient"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 70
+
#undef DPTF_ENABLE_FAN_CONTROL
#undef DPTF_ENABLE_CHARGER
@@ -33,8 +41,14 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
- /* CPU Effect on Board */
+ /* CPU Throttle Effect on Skin (TSR0) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on DDR (TSR1) */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on Ambient (TSR2) */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
})
Name (MPPC, Package ()
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
index ff59e3ce72..459fb67875 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
@@ -16,16 +16,24 @@
#define DPTF_CPU_PASSIVE 80
#define DPTF_CPU_CRITICAL 100
+/* Skin Sensor for CPU VR temperature monitor */
#define DPTF_TSR0_SENSOR_ID 1
-#define DPTF_TSR0_SENSOR_NAME "Thermal 1"
+#define DPTF_TSR0_SENSOR_NAME "Skin"
#define DPTF_TSR0_PASSIVE 55
-#define DPTF_TSR0_CRITICAL 80
+#define DPTF_TSR0_CRITICAL 70
+/* Memory Sensor for DDR temperature monitor */
#define DPTF_TSR1_SENSOR_ID 2
-#define DPTF_TSR1_SENSOR_NAME "Thermal 2"
+#define DPTF_TSR1_SENSOR_NAME "DDR"
#define DPTF_TSR1_PASSIVE 55
#define DPTF_TSR1_CRITICAL 80
+/* M.2 Sensor for Ambient temperature monitor */
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "Ambient"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 70
+
#undef DPTF_ENABLE_FAN_CONTROL
#undef DPTF_ENABLE_CHARGER
@@ -33,8 +41,14 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
- /* CPU Effect on Board */
+ /* CPU Throttle Effect on Skin (TSR0) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on DDR (TSR1) */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on Ambient (TSR2) */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
})
Name (MPPC, Package ()