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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-05-09 16:37:30 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:02:54 +0000
commit309ccf74dd7c25874572c6a62ffc7042dcdadc66 (patch)
tree7b1e79798c0607ef794bb4cd24c575713a552db5 /src/mainboard/google/sarien
parent7d054bd38f5cfe36f6abd4f4422c463243bc3749 (diff)
downloadcoreboot-309ccf74dd7c25874572c6a62ffc7042dcdadc66.tar.xz
cannonlake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Cannonlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on drallion system Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/sarien')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb8
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb8
2 files changed, 10 insertions, 6 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index d1d9b038b2..a84e73a826 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -31,12 +31,14 @@ chip soc/intel/cannonlake
register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1"
- register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "satapwroptimize" = "1"
- register "tdp_pl1_override" = "25"
- register "tdp_pl2_override" = "51"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 25,
+ .tdp_pl2_override = 51,
+ .psys_pmax = 140,
+ }"
register "Device4Enable" = "1"
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index b2aa8d5e8d..09b4240993 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -42,9 +42,11 @@ chip soc/intel/cannonlake
register "SlowSlewRateForGt" = "2"
register "SlowSlewRateForSa" = "2"
register "SlowSlewRateForFivr" = "2"
- register "tdp_pl1_override" = "15"
- register "tdp_pl2_override" = "51"
- register "psys_pmax" = "136"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 51,
+ .psys_pmax = 136,
+ }"
register "Device4Enable" = "1"
# Enable eDP device
register "DdiPortEdp" = "1"