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authorIvy Jian <ivy_jian@compal.corp-partner.google.com>2020-06-16 15:22:47 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-07-23 17:05:38 +0000
commit311ddbd193dd0702b8f506ace32facf6402b6e8e (patch)
tree737c181515da861e38fb56868169af1ccf2c5bd5 /src/mainboard/google/sarien
parentd54c9b0fef7289c948070d98dc9aeae56072db68 (diff)
downloadcoreboot-311ddbd193dd0702b8f506ace32facf6402b6e8e.tar.xz
mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien. BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard/google/sarien')
-rw-r--r--src/mainboard/google/sarien/Kconfig1
-rw-r--r--src/mainboard/google/sarien/Makefile.inc1
-rw-r--r--src/mainboard/google/sarien/mainboard.c55
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb8
4 files changed, 65 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index df5e5b8420..53b92439b0 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -2,6 +2,7 @@
config BOARD_GOOGLE_BASEBOARD_SARIEN
def_bool n
select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_GENERIC_BH720
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA
diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc
index eea7f472e6..e7bfc53aa0 100644
--- a/src/mainboard/google/sarien/Makefile.inc
+++ b/src/mainboard/google/sarien/Makefile.inc
@@ -2,6 +2,7 @@
bootblock-y += bootblock.c
+ramstage-y += mainboard.c
ramstage-y += ramstage.c
ramstage-y += sku.c
diff --git a/src/mainboard/google/sarien/mainboard.c b/src/mainboard/google/sarien/mainboard.c
new file mode 100644
index 0000000000..5399e6cd78
--- /dev/null
+++ b/src/mainboard/google/sarien/mainboard.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <drivers/generic/bayhub/bh720.h>
+#include <string.h>
+
+void board_bh720(struct device *dev)
+{
+ u32 sdbar;
+ u32 bh720_pcr_data;
+
+ printk(BIOS_DEBUG, "mainboard: %s init\n", __func__);
+ sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
+
+ /* Enable Memory Access Function */
+ write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
+ write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000);
+ write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
+
+ /* Set EMMC VCCQ 1.8V PCR 0x308[4] */
+ write32((void *)(sdbar + BH720_MEM_RW_ADR),
+ BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING);
+ bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
+ write32((void *)(sdbar + BH720_MEM_RW_DATA),
+ bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V);
+ write32((void *)(sdbar + BH720_MEM_RW_ADR),
+ BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
+
+ /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */
+ write32((void *)(sdbar + BH720_MEM_RW_ADR),
+ BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL);
+ bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
+ bh720_pcr_data &= 0x0000FFFF;
+ bh720_pcr_data |= 0x2510 << 16;
+ write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data);
+ write32((void *)(sdbar + BH720_MEM_RW_ADR),
+ BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL);
+
+ /* Use PLL Base clock PCR 0x3E4[22] = 1 */
+ write32((void *)(sdbar + BH720_MEM_RW_ADR),
+ BH720_MEM_RW_READ | BH720_PCR_CSR);
+ bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
+ write32((void *)(sdbar + BH720_MEM_RW_DATA),
+ bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL);
+ write32((void *)(sdbar + BH720_MEM_RW_ADR),
+ BH720_MEM_RW_WRITE | BH720_PCR_CSR);
+
+ /* Disable Memory Access */
+ write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
+ write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
+ write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
+}
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 09b4240993..1a8e62454b 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -395,12 +395,20 @@ chip soc/intel/cannonlake
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on end # PCI Express Port 8
device pci 1d.0 on
+ chip drivers/generic/bayhub
+ register "power_saving" = "1"
+ device pci 00.0 on end
+ end
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on
+ chip drivers/generic/bayhub
+ register "power_saving" = "1"
+ device pci 00.0 on end
+ end
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0