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author | Matt DeVillier <matt.devillier@gmail.com> | 2016-11-27 02:19:02 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2016-12-05 19:06:47 +0100 |
commit | c12e5ae1a5d809a4b74774d28a1c231591400bd3 (patch) | |
tree | 0c74e22f3e1f75a34b96ddf90be0fba2702e2efa /src/mainboard/google/slippy/chromeos.fmd | |
parent | b5a74d6ca21139ddcb9a613f810338b6e97f27b9 (diff) | |
download | coreboot-c12e5ae1a5d809a4b74774d28a1c231591400bd3.tar.xz |
Add/Combine Haswell Chromebooks using variant board scheme
Combine existing boards google/falco and google/peppy with new
ChromeOS devices leon and wolf, using their common reference board
(slippy) as a base.
Chromium sources used:
firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...]
firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode]
firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use ACPI (vs PCI) mode
- I2C device ACPI entries adjusted as per above
- I2C devices set to use level (vs edge) interrupt triggering
- XHCI finalization enabled in devicetree
- HDA verb entries use simplified macro entry format
Existing google/falco and google/peppy boards will be removed in a
subsequent commit.
Variant setup modeled after google/beltino
Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17621
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/slippy/chromeos.fmd')
-rw-r--r-- | src/mainboard/google/slippy/chromeos.fmd | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd new file mode 100644 index 0000000000..0c05ce95ce --- /dev/null +++ b/src/mainboard/google/slippy/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + RW_SECTION_A@0x0 0xf0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0xdffc0 + RW_FWID_A@0xeffc0 0x40 + } + RW_SECTION_B@0xf0000 0xf0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0xdffc0 + RW_FWID_B@0xeffc0 0x40 + } + RW_MRC_CACHE@0x1e0000 0x10000 + RW_ELOG@0x1f0000 0x4000 + RW_SHARED@0x1f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x1f8000 0x2000 + RW_UNUSED@0x1fa000 0x6000 + RW_LEGACY(CBFS)@0x200000 0x200000 + WP_RO@0x400000 0x200000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x1f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x6f000 + COREBOOT(CBFS)@0x70000 0x180000 + } + } + } +} |