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author | Matt DeVillier <matt.devillier@gmail.com> | 2016-11-27 02:19:02 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2016-12-05 19:06:47 +0100 |
commit | c12e5ae1a5d809a4b74774d28a1c231591400bd3 (patch) | |
tree | 0c74e22f3e1f75a34b96ddf90be0fba2702e2efa /src/mainboard/google/slippy/dsdt.asl | |
parent | b5a74d6ca21139ddcb9a613f810338b6e97f27b9 (diff) | |
download | coreboot-c12e5ae1a5d809a4b74774d28a1c231591400bd3.tar.xz |
Add/Combine Haswell Chromebooks using variant board scheme
Combine existing boards google/falco and google/peppy with new
ChromeOS devices leon and wolf, using their common reference board
(slippy) as a base.
Chromium sources used:
firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...]
firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode]
firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use ACPI (vs PCI) mode
- I2C device ACPI entries adjusted as per above
- I2C devices set to use level (vs edge) interrupt triggering
- XHCI finalization enabled in devicetree
- HDA verb entries use simplified macro entry format
Existing google/falco and google/peppy boards will be removed in a
subsequent commit.
Variant setup modeled after google/beltino
Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17621
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/slippy/dsdt.asl')
-rw-r--r-- | src/mainboard/google/slippy/dsdt.asl | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl new file mode 100644 index 0000000000..56771c2886 --- /dev/null +++ b/src/mainboard/google/slippy/dsdt.asl @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <cpu/intel/haswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + Scope (\_SB.PCI0.RP01) + { + Device (WLAN) + { + Name (_ADR, Zero) + } + } + + // Mainboard specific + #include <variant/acpi/mainboard.asl> + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> +} |