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authorDuncan Laurie <dlaurie@chromium.org>2013-04-29 15:10:31 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-11-24 06:15:12 +0100
commitcf72d91613eef7a2ff7ed2145cd8baefff35eb16 (patch)
tree6d52eb31d1fe22b07aeed9303fa52c197982951a /src/mainboard/google/slippy/dsdt.asl
parent7797ffa1bebfefde0076383a12f620897e5ef81a (diff)
downloadcoreboot-cf72d91613eef7a2ff7ed2145cd8baefff35eb16.tar.xz
slippy: Initial mainboard commit
Change-Id: I33876b90902d4a08d760eb482b08ba41be6e3695 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49531 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4147 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl
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+++ b/src/mainboard/google/slippy/dsdt.asl
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+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // CPU
+ #include <cpu/intel/haswell/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/haswell/acpi/haswell.asl>
+ #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ }
+ }
+
+ // Thermal handler
+ #include "acpi/thermal.asl"
+
+ // Chrome OS specific
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ // Chipset specific sleep states
+ #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+}