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author | Furquan Shaikh <furquan@google.com> | 2013-07-22 16:18:31 -0700 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 08:04:10 +0100 |
commit | 6b19071ffb89dbb68196b7f3b088d87d4fad9e80 (patch) | |
tree | cb68ceaff1796a7798288eba1f6472154642b76a /src/mainboard/google/slippy/gma.c | |
parent | 3d9b5a29317b9df63698abbcf743ff4d15b2892a (diff) | |
download | coreboot-6b19071ffb89dbb68196b7f3b088d87d4fad9e80.tar.xz |
FUI: Fill in link_m and link_n values
... based on the EDID detailed timing values for
pixel_clock and link_clock.
Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n
respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond
to data_m and data_n respectively.
Calculations are based on the intel_link_compute_m_n from linux kernel.
Currently, the value for 0x6f030 does not come up right with our calculations.
Hence, set to hard-coded value.
Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e
Reviewed-on: https://gerrit.chromium.org/gerrit/62915
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4381
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/slippy/gma.c')
-rw-r--r-- | src/mainboard/google/slippy/gma.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index 39072186e0..52a7b0b4e8 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -288,6 +288,12 @@ void dp_init_dim_regs(struct intel_dp *dp) dp->pfa_sz = (edid->ha << 16) | (edid->va); + intel_dp_compute_m_n(dp->bpp, + dp->lane_count, + dp->edid.pixel_clock, + dp->edid.link_clock, + &dp->m_n); + printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride); printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal); printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank); @@ -299,6 +305,26 @@ void dp_init_dim_regs(struct intel_dp *dp) printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos); printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl); printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz); + printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m); + printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n); + printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m); + printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m); + printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n); +} + +int intel_dp_bw_code_to_link_rate(u8 link_bw); + +int intel_dp_bw_code_to_link_rate(u8 link_bw) +{ + switch (link_bw) { + case DP_LINK_BW_1_62: + default: + return 162000; + case DP_LINK_BW_2_7: + return 270000; + case DP_LINK_BW_5_4: + return 540000; + } } int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, @@ -366,6 +392,10 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); + dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw); + + printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock); + dp_init_dim_regs(dp); /* more undocumented stuff. */ |