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authorFurquan Shaikh <furquan@google.com>2013-07-31 16:47:31 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 13:26:55 +0100
commitdb3157cfee6881d8095c4f96cd1fa5d5da9a5c68 (patch)
treec25d2542d6880b8a5c38fe0bc59e7553c7725a60 /src/mainboard/google/slippy
parentd0a81f75342508449d13fd05305864413470e0c9 (diff)
downloadcoreboot-db3157cfee6881d8095c4f96cd1fa5d5da9a5c68.tar.xz
Add cpu transcoder attribute to intel dp
Also, used this attribute in the calculation of htotal and other registers Added intel_dp_* functions for m,n registers and dimension register calculations Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a Reviewed-on: https://gerrit.chromium.org/gerrit/64001 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4422 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/slippy')
-rw-r--r--src/mainboard/google/slippy/gma.c3
-rw-r--r--src/mainboard/google/slippy/i915io.c27
2 files changed, 9 insertions, 21 deletions
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 99dcbc56b6..026bba1583 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -295,6 +295,9 @@ void dp_init_dim_regs(struct intel_dp *dp)
dp->lane_count,
dp->pfa_sz);
+ dp->transcoder = intel_ddi_get_transcoder(dp->port,
+ dp->pipe);
+
intel_dp_compute_m_n(dp->bpp,
dp->lane_count,
dp->edid.pixel_clock,
diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c
index e3f7f301cf..cf57430926 100644
--- a/src/mainboard/google/slippy/i915io.c
+++ b/src/mainboard/google/slippy/i915io.c
@@ -115,27 +115,12 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
unpack_aux(auxout, &msg[0], 4);
intel_dp_aux_ch(dp, msg, 4, auxin, 0);
- /* undocumented. */
- io_i915_write32(0x7e4a0000,0x6f030);
- /* io_i915_write32(0x00800000,0x6f034); */
- /* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important.
- However, with our formula we always see values 0x7e43yyyy (1366 panel) and
- 0x7e42yyy (1280 panel) */
- /* io_i915_write32(TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m,0x6f030); */
- io_i915_write32(dp->m_n.gmch_n,0x6f034);
- io_i915_write32(dp->m_n.link_m,0x6f040);
- io_i915_write32(dp->m_n.link_n,0x6f044);
-
- /* leave as is for now. */
- io_i915_write32(dp->htotal,0x6f000);
- io_i915_write32(dp->hblank,0x6f004);
- io_i915_write32(dp->hsync,0x6f008);
- io_i915_write32(dp->vtotal,0x6f00c);
- io_i915_write32(dp->vblank,0x6f010);
- io_i915_write32(dp->vsync,0x6f014);
- io_i915_write32(dp->pipesrc,_PIPEASRC);
- io_i915_write32(0x00000000,0x7f008);
- io_i915_write32(0x00000000,_TRANSACONF);
+ intel_dp_set_m_n_regs(dp);
+
+ intel_dp_set_resolution(dp);
+ io_i915_write32(dp->pipesrc,PIPESRC(dp->pipe));
+ io_i915_write32(0x00000000, PIPECONF(dp->transcoder));
+ io_i915_write32(0x00000000, PCH_TRANSCONF(dp->pipe));
io_i915_write32(0x20000000,PORT_CLK_SEL_A);
io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x14000000,_DSPACNTR);