diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 14:28:48 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 09:57:34 +0000 |
| commit | c05c2b3fb25ca42a75ecc987178c298f7fe0ead5 (patch) | |
| tree | ab91d94d7564cdf16191f2335294877dc8e7fc5a /src/mainboard/google/slippy | |
| parent | 14c4f4f43cc5a1cdcb2769357cee7e00fd620e93 (diff) | |
| download | coreboot-c05c2b3fb25ca42a75ecc987178c298f7fe0ead5.tar.xz | |
haswell boards: Fix writes to 16-bit DxxIR registers
The DxxIR (Device xx Interrupt Route) registers in RCBA are 16-bit wide,
so do not use 32-bit operations to program them.
Note that the DxxIP (Device xx Interrupt Pin) registers are 32-bit, so
using 32-bit operations on them is correct.
Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/google/slippy')
| -rw-r--r-- | src/mainboard/google/slippy/romstage.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index c7240491cd..a24f5c4dcd 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -33,14 +33,14 @@ void mainboard_config_rcba(void) RCBA32(D20IP) = (INTA << D20IP_XHCI); /* Device interrupt route registers */ - RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ - RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ - RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ - RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ - RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ - RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ - RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ - RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ + RCBA16(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA16(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA16(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA16(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ } void mainboard_romstage_entry(void) |