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| author | Matt DeVillier <matt.devillier@gmail.com> | 2015-04-30 01:19:16 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-30 17:50:47 +0200 |
| commit | 31769d99da7f97150ddc30174c7cc315ca6e7b1f (patch) | |
| tree | 9ad50867ffea7f90491754e1638f3f6e4bc0241c /src/mainboard/google/slippy | |
| parent | 40e2004abf4f763f38bfb12069b683554644734a (diff) | |
| download | coreboot-31769d99da7f97150ddc30174c7cc315ca6e7b1f.tar.xz | |
cpu/intel/haswell: remove dependency on socket_rpga989
Remove dependency of Haswell on cpu/intel/socket_rpga989 code,
which is a carry-over from Sandy Bridge/Ivy Bridge and older
coreboot conventions where features were structured around socket types.
Add CPU-specific options to Kconfig and required subdirs to
Makefile.inc which are curently included with socket_rpga989.
TEST=successfully built and booted on google/panther
Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10037
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/slippy')
| -rw-r--r-- | src/mainboard/google/slippy/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/slippy/devicetree.cb | 4 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 48e58257b7..2857c0a95f 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_SLIPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 06ca93c9f4..f50882cc6d 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end |