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| author | Julius Werner <jwerner@chromium.org> | 2017-04-14 15:39:23 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-05-30 22:18:26 +0200 |
| commit | c25b2a18fa42f26a799c55c5e463ecb5f4e4c89e (patch) | |
| tree | 2b90f696a57935642e3acd86dcdb92f9c23b595a /src/mainboard/google/smaug | |
| parent | baa3e70084bac00885667b20efde3e69901cda70 (diff) | |
| download | coreboot-c25b2a18fa42f26a799c55c5e463ecb5f4e4c89e.tar.xz | |
tegra210: Remove fake cpu_reset()
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's
pointless to pretend there is one. Most ARM SoCs/boards only define
hard_reset() at the moment anyway, so let's stick with that.
Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/mainboard/google/smaug')
| -rw-r--r-- | src/mainboard/google/smaug/pmic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index cba555a5e7..25e870a123 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -46,8 +46,8 @@ static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val, if (i2c_writeb(bus, chip, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); - /* Reset the SoC on any PMIC write error */ - cpu_reset(); + /* Reset the board on any PMIC write error */ + hard_reset(); } else { if (delay) udelay(500); |