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| author | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-04 16:39:35 -0800 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2013-03-06 22:04:51 +0100 |
| commit | f4861df1e749885ec68ea0f17a3589aa6e79d13f (patch) | |
| tree | 06f1222e4fc99f4aa34de96715129dee101e6edb /src/mainboard/google/snow/romstage.c | |
| parent | 3914a316c3d3ab1ba45fe33394f37aaefdc62d61 (diff) | |
| download | coreboot-f4861df1e749885ec68ea0f17a3589aa6e79d13f.tar.xz | |
google/snow: Change MMC0 to work in 8 bit mode.
The MMC0 on google/snow can run in 8 bit mode. To simplify driver development,
we thought disabling it (using zero, which runs in 1-bit / 4-bit mode) may help.
However, after some experiments in payload drivers, setting pinmux to 8 bit mode
can still allow MMC to run in 1-bit / 4-bit mode, so it's pretty safe to enable
8 bit mode by default for better performance.
Verified to boot on google/snow, and got MMC0 working.
Change-Id: Ic0acc723fe6a8aecf373429d3801beadd70815d9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2585
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/mainboard/google/snow/romstage.c')
| -rw-r--r-- | src/mainboard/google/snow/romstage.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7e1cd5797b..25c0846a07 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -53,7 +53,7 @@ static int board_wakeup_permitted(void) #endif static void initialize_s5p_mshc(void) { - /* MMC0: Fixed, support 8 bit mode, connected with GPIO. */ + /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ if (clock_set_mshci(PERIPH_ID_SDMMC0)) printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n"); if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { @@ -61,9 +61,7 @@ static void initialize_s5p_mshc(void) { } gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE); gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X); - /* TODO(hungte) Change 0 to PINMUX_FLAG_8BIT_MODE when the s5p_mshc - * driver is ready. */ - exynos_pinmux_config(PERIPH_ID_SDMMC0, 0); + exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); /* MMC2: Removable, 4 bit mode, no GPIO. */ clock_set_mshci(PERIPH_ID_SDMMC2); |