summaryrefslogtreecommitdiff
path: root/src/mainboard/google/snow
diff options
context:
space:
mode:
authorJulius Werner <jwerner@chromium.org>2013-08-27 15:48:32 -0700
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-08-13 00:04:14 +0200
commitb8fad3d02986222fa162d455eca2ffe807b6a15a (patch)
treef6beaf474faa9f4a9a4a611abb52774e7d0906ed /src/mainboard/google/snow
parent4498f6a6e57aa3bc1ed9449e3ad153b1a60c4eb6 (diff)
downloadcoreboot-b8fad3d02986222fa162d455eca2ffe807b6a15a.tar.xz
arm: libpayload: Add cache coherent DMA memory definition and management
This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/snow')
-rw-r--r--src/mainboard/google/snow/mainboard.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index d209a762fc..dfaf81d537 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -46,6 +46,10 @@
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
+/* Arbitrary range of DMA memory for depthcharge's drivers */
+#define DMA_START (0x77300000)
+#define DMA_SIZE (0x00100000)
+
static struct edid edid = {
.ha = 1366,
.va = 768,
@@ -320,6 +324,7 @@ static void mainboard_enable(device_t dev)
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
+ mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_invalidate_all();
dcache_mmu_enable();
@@ -342,3 +347,14 @@ struct chip_operations mainboard_ops = {
.name = "Samsung/Google ARM Chromebook",
.enable_dev = mainboard_enable,
};
+
+void lb_board(struct lb_header *header)
+{
+ struct lb_range *dma;
+
+ dma = (struct lb_range *)lb_new_record(header);
+ dma->tag = LB_TAB_DMA;
+ dma->size = sizeof(*dma);
+ dma->range_start = (intptr_t)DMA_START;
+ dma->range_size = DMA_SIZE;
+}