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authorHung-Te Lin <hungte@chromium.org>2013-03-01 10:34:04 +0800
committerRonald G. Minnich <rminnich@gmail.com>2013-03-01 06:53:57 +0100
commitf12e56181788387c560c9b8d0f3d61fce4a4333a (patch)
treeb136e09de17cf327df097e2cef0b9da539d42c73 /src/mainboard/google/snow
parent27bd64a8be3b4e3bff883377e3a0f5ae55d176c7 (diff)
downloadcoreboot-f12e56181788387c560c9b8d0f3d61fce4a4333a.tar.xz
armv7/snow: Add S5P MSHC initialization in ROM stage.
The SD/MMC interface on Exynos 5250 must be first configured with, GPIO, and pinmux settings before it can be detected and used in ramstage / payload. Verified on armv7/snow and successfully boot into ramstage. Change-Id: I26669eaaa212ab51ca72e8b7712970639a24e5c5 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2561 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google/snow')
-rw-r--r--src/mainboard/google/snow/romstage.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 9891011fe4..7e1cd5797b 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -24,8 +24,10 @@
#include <cbfs.h>
#include <common.h>
+#include <arch/gpio.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/dmc.h>
+#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/periph.h>
#include <cpu/samsung/exynos5250/clock_init.h>
@@ -35,6 +37,8 @@
#include "mainboard.h"
+#define MMC0_GPIO_PIN (58)
+
#if 0
static int board_wakeup_permitted(void)
{
@@ -48,6 +52,24 @@ static int board_wakeup_permitted(void)
}
#endif
+static void initialize_s5p_mshc(void) {
+ /* MMC0: Fixed, support 8 bit mode, connected with GPIO. */
+ if (clock_set_mshci(PERIPH_ID_SDMMC0))
+ printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n");
+ if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
+ printk(BIOS_CRIT, "Unable to power on SDMMC0.\n");
+ }
+ gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE);
+ gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X);
+ /* TODO(hungte) Change 0 to PINMUX_FLAG_8BIT_MODE when the s5p_mshc
+ * driver is ready. */
+ exynos_pinmux_config(PERIPH_ID_SDMMC0, 0);
+
+ /* MMC2: Removable, 4 bit mode, no GPIO. */
+ clock_set_mshci(PERIPH_ID_SDMMC2);
+ exynos_pinmux_config(PERIPH_ID_SDMMC2, 0);
+}
+
void main(void)
{
struct mem_timings *mem;
@@ -84,6 +106,8 @@ void main(void)
mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
+ initialize_s5p_mshc();
+
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);