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| author | Patrick Rudolph <siro@das-labor.org> | 2016-03-15 07:44:49 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-21 23:13:13 +0100 |
| commit | 5c10abeb734d8adee217bc5ed1edcb042064d239 (patch) | |
| tree | 5ebbe9fae4f0c73250d294068d8d80f2c17ca837 /src/mainboard/google/stout/Kconfig | |
| parent | ade606df162c5153268ed7ec46c376132dc263a5 (diff) | |
| download | coreboot-5c10abeb734d8adee217bc5ed1edcb042064d239.tar.xz | |
nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS
Set MMCONF_BASE_ADDRESS to 0xf8000000.
It was already done for some boards, but not all.
The sandybridge chipset code assumes 64 pci buses behind MMCONF.
Therefore, only 64MiB of physical address space is required.
Increasing the address allows to use additional 128MiB of MMIO
space and to use the Intel IGD and a PEG at the same time.
Previously it wasn't possible to use both at the same time,
as two 256MiB areas won't fit into MMIO space.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
* Onboard GPU Intel IvyBridge Desktop
* PEG GPU AMD RV770
Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Diffstat (limited to 'src/mainboard/google/stout/Kconfig')
| -rw-r--r-- | src/mainboard/google/stout/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 197099e50c..0aafc48521 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int |