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author | Angel Pons <th3fanbus@gmail.com> | 2021-04-02 22:55:00 +0200 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2021-04-05 13:16:43 +0000 |
commit | 5304ce108e1f8fceff543543be092253cf09edb0 (patch) | |
tree | 3c12a6a8350eac9da4dee56d4065f39496c69ede /src/mainboard/google/stout | |
parent | f2e8660fa24b9e153967cc7e01486793806f9779 (diff) | |
download | coreboot-5304ce108e1f8fceff543543be092253cf09edb0.tar.xz |
nb/intel/sandybridge: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/stout')
-rw-r--r-- | src/mainboard/google/stout/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 5461b15dd9..73dce98ed0 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -33,8 +33,6 @@ chip northbridge/intel/sandybridge end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge |