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authorVladimir Serbinenko <phcoder@gmail.com>2014-01-11 07:46:50 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-01-12 18:03:23 +0100
commit6d6298dddc4147e7a1df6c51cb97b3d94e9c4584 (patch)
treee51953d0c3691a6ae4ff491981d7e77f0d3aff7a /src/mainboard/google/stout
parent2dd601efafb54433e1bbf60f3936eeba7ef353e2 (diff)
downloadcoreboot-6d6298dddc4147e7a1df6c51cb97b3d94e9c4584.tar.xz
ibexpeak / bd82x6x: Make SATA mode user-visible option.
Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/stout')
-rw-r--r--src/mainboard/google/stout/cmos.layout5
-rw-r--r--src/mainboard/google/stout/devicetree.cb2
2 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout
index afdd3c66ca..b7320b5b99 100644
--- a/src/mainboard/google/stout/cmos.layout
+++ b/src/mainboard/google/stout/cmos.layout
@@ -85,7 +85,8 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
+411 1 e 8 sata_mode
+#412 4 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
@@ -131,6 +132,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 6e02020890..653d3fe424 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge
register "gpi1_routing" = "1"
register "gpi6_routing" = "2"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x3"
# Set max SATA speed to 3.0 Gb/s
register "sata_interface_speed_support" = "0x2"