summaryrefslogtreecommitdiff
path: root/src/mainboard/google/stout
diff options
context:
space:
mode:
authorVladimir Serbinenko <phcoder@gmail.com>2015-05-18 10:29:06 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2015-05-27 22:23:05 +0200
commit0e90dae584c506b06e7bf3d89064a64db04132bb (patch)
tree83876d4f6e39e432789c0bcdb6384068bdcd566b /src/mainboard/google/stout
parent40772a0b5afc7d82a213b005905e2d9e71a6328e (diff)
downloadcoreboot-0e90dae584c506b06e7bf3d89064a64db04132bb.tar.xz
Move TPM code out of chromeos
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/stout')
-rw-r--r--src/mainboard/google/stout/Kconfig1
-rw-r--r--src/mainboard/google/stout/romstage.c10
2 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
index ec03d8761e..eca83da637 100644
--- a/src/mainboard/google/stout/Kconfig
+++ b/src/mainboard/google/stout/Kconfig
@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index ee6ca4f520..31b61e2d72 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -40,9 +40,7 @@
#include <halt.h>
#include "gpio.h"
#include <bootmode.h>
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <tpm.h>
#include <cbfs.h>
#include <ec/quanta/it8518/ec.h>
#include "ec.h"
@@ -251,8 +249,8 @@ void main(unsigned long bist)
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ if (CONFIG_LPC_TPM) {
+ init_tpm(boot_mode == 2);
+ }
timestamp_add_now(TS_END_ROMSTAGE);
}