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authorArthur Heymans <arthur@aheymans.xyz>2019-01-21 17:48:55 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:57:56 +0000
commitb3f2323e84a8ed47f9cd6aa4d2b885d58da58d97 (patch)
tree1574b51da9ceb7b8f453f2d9cb7c77088448b829 /src/mainboard/google/stout
parent1a9034cca606ad7e2c1202c190a329bd8821afb4 (diff)
downloadcoreboot-b3f2323e84a8ed47f9cd6aa4d2b885d58da58d97.tar.xz
mb/*/*/devicetree.cb: Make sandybridge devicetree uniform
This is a merely cosmetic change. Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/google/stout')
-rw-r--r--src/mainboard/google/stout/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 0fdb55ebdb..31407820a1 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge
end
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
- device lapic 0xACAC off end
+ device lapic 0xacac off end
register "tcc_offset" = "5" # TCC of 95C