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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-11-01 19:55:48 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-12-31 17:36:06 +0100 |
| commit | 4f3d400a30247b7795254517078529d070f4129f (patch) | |
| tree | f055a06ed392b4b7f917436477bfd13b0b47e950 /src/mainboard/google/urara | |
| parent | 3218e794ba567ee7b51f2206e01f86f1d9358358 (diff) | |
| download | coreboot-4f3d400a30247b7795254517078529d070f4129f.tar.xz | |
imgtec/pistachio: disable default RPU gate register values
The RPU Clock register defaults to on for all clocks.
This is modified to OFF, and the MIPS clock control modified to ON,
by default. This is because the linux kernel will manage the
clocks at all times, but the RPU can only disable clocks if the WIFI
module has been loaded.
Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/urara')
| -rw-r--r-- | src/mainboard/google/urara/bootblock.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 7775916f11..121f35df14 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -190,6 +190,14 @@ static void bootblock_mainboard_init(void) if (ret != CLOCKS_OK) return; + /* + * Move peripheral clock control from RPU to MIPS. + * The RPU gate register is not managed in Linux so disable its default + * values and assign MIPS gate register the default values. + * *Note*: All unused clocks will be gated by Linux + */ + setup_clk_gate_defaults(); + /* Setup SPIM1 MFIOs */ spim1_mfio_setup(); /* Setup UART1 clock and MFIOs |