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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-20 20:30:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-22 12:18:41 +0000 |
| commit | a9506dbaf410d9b2d297661f51f0e0b9842170e1 (patch) | |
| tree | b442dc8f162549abb0e11377c80bc624a69e896a /src/mainboard/google/urara | |
| parent | 9c8044bdcd2aa77d8a8092b270ca36fd3aa23b87 (diff) | |
| download | coreboot-a9506dbaf410d9b2d297661f51f0e0b9842170e1.tar.xz | |
arch/mips: Fix <arch/mmio.h> prototypes
These signatures need to be consistent across different
architectures.
Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/urara')
| -rw-r--r-- | src/mainboard/google/urara/bootblock.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 682bef7729..5b0b29d0f7 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -66,10 +66,10 @@ static void pad_drive_strength(u32 pad, drive_strength strength) /* Set drive strength value */ drive_strength_shift = (pad % 16) * PAD_DRIVE_STRENGTH_LENGTH; - reg = read32(PAD_DRIVE_STRENGTH_ADDR(pad / 16)); + reg = read32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16)); reg &= ~(PAD_DRIVE_STRENGTH_MASK << drive_strength_shift); reg |= strength << drive_strength_shift; - write32(PAD_DRIVE_STRENGTH_ADDR(pad / 16), reg); + write32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16), reg); } static void uart1_mfio_setup(void) @@ -83,7 +83,7 @@ static void uart1_mfio_setup(void) * is no need to set up a function number in the corresponding * function select register. */ - reg = read32(GPIO_BIT_EN_ADDR(3)); + reg = read32_x(GPIO_BIT_EN_ADDR(3)); mfio_mask = 1 << (UART1_RXD_MFIO % 16); mfio_mask |= 1 << (UART1_TXD_MFIO % 16); /* Clear relevant bits */ @@ -93,7 +93,7 @@ static void uart1_mfio_setup(void) * in order to be able to modify the chosen pins */ reg |= mfio_mask << 16; - write32(GPIO_BIT_EN_ADDR(3), reg); + write32_x(GPIO_BIT_EN_ADDR(3), reg); } static void spim1_mfio_setup(void) @@ -106,7 +106,7 @@ static void spim1_mfio_setup(void) * is no need to set up a function number in the corresponding * function select register. */ - reg = read32(GPIO_BIT_EN_ADDR(0)); + reg = read32_x(GPIO_BIT_EN_ADDR(0)); /* Disable GPIO for SPIM1 MFIOs */ mfio_mask = 1 << (SPIM1_D0_TXD_MFIO % 16); @@ -123,7 +123,7 @@ static void spim1_mfio_setup(void) * in order to be able to modify the chosen pins */ reg |= mfio_mask << 16; - write32(GPIO_BIT_EN_ADDR(0), reg); + write32_x(GPIO_BIT_EN_ADDR(0), reg); /* Set drive strength to maximum for these MFIOs */ pad_drive_strength(SPIM1_CS0_MFIO, DRIVE_STRENGTH_12mA); @@ -142,7 +142,7 @@ static void i2c_mfio_setup(int interface) /* * Disable GPIO for I2C MFIOs */ - reg = read32(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16)); + reg = read32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16)); mfio_mask = 1 << (I2C_DATA_MFIO(interface) % 16); mfio_mask |= 1 << (I2C_CLK_MFIO(interface) % 16); /* Clear relevant bits */ @@ -152,7 +152,7 @@ static void i2c_mfio_setup(int interface) * in order to be able to modify the chosen pins */ reg |= mfio_mask << 16; - write32(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16), reg); + write32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16), reg); /* for I2C0 and I2C1: * Set bits to 0 (clear) which is the primary function @@ -162,12 +162,12 @@ static void i2c_mfio_setup(int interface) */ if (interface > 1) return; - reg = read32(PADS_FUNCTION_SELECT0_ADDR); + reg = read32_x(PADS_FUNCTION_SELECT0_ADDR); reg &= ~(I2C_DATA_FUNCTION_MASK << I2C_DATA_FUNCTION_OFFSET(interface)); reg &= ~(I2C_CLK_FUNCTION_MASK << I2C_CLK_FUNCTION_OFFSET(interface)); - write32(PADS_FUNCTION_SELECT0_ADDR, reg); + write32_x(PADS_FUNCTION_SELECT0_ADDR, reg); } static void bootblock_mainboard_init(void) |