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authorJulius Werner <jwerner@chromium.org>2015-08-28 14:34:09 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-08 11:36:44 +0000
commitdd07ef2acd65df0f64a34545c6dd85060de4659f (patch)
treeb72675c76e46f76a24068e472041d11908eb4b89 /src/mainboard/google/veyron/Kconfig
parent736a4a2a1728ea0e28f96c1a19d6be9544b58f94 (diff)
downloadcoreboot-dd07ef2acd65df0f64a34545c6dd85060de4659f.tar.xz
veyron: Unify identical mainboards
This patch removes a lot of code duplication between the virtually identical Veyron Chromebook variants by merging the code into a single directory and handling the different names solely within Kconfig. This also allows us to easily add all the other Chromebook variants that have only been kept in Google's firmware branch to avoid cluttering coreboot too much, making it possible to build these boards with upstream coreboot out of the box. The only effective change this will have on the affected boards is removing quirks for early board revisions (since revision numbers differ between variants). Since all those quirks concerned early pre-MP revisions, I doubt this will bother anyone (and the old code is still available through the Google firmware branch if anyone needs it). It will also expand a recent fix in Jerry that increased an LCD power-on delay to make it compatible with another kind of panel to all boards, which is probably not a bad idea anyway. Leaving all non-Chromebook boards as they are for now since they often contain more extensive differences. BRANCH=None BUG=None TEST=Booted Jerry. Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9 Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296053 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11555 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/veyron/Kconfig')
-rw-r--r--src/mainboard/google/veyron/Kconfig88
1 files changed, 88 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
new file mode 100644
index 0000000000..c474bd652f
--- /dev/null
+++ b/src/mainboard/google/veyron/Kconfig
@@ -0,0 +1,88 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards
+ def_bool n
+
+if BOARD_GOOGLE_VEYRON
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ID_AUTO
+ select COMMON_CBFS_SPI_WRAPPER
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_SPI
+ select RAM_CODE_SUPPORT
+ select SOC_ROCKCHIP_RK3288
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_DO_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_CHROMEOS
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_HARD_RESET
+ select SPI_FLASH
+ select SPI_FLASH_GIGADEVICE
+ select SPI_FLASH_WINBOND
+
+config CHROMEOS
+ select CHROMEOS_VBNV_EC
+ select EC_SOFTWARE_SYNC
+ select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+ string
+ default google/veyron
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Veyron"
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ hex
+ default 0
+
+config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
+ int
+ default 100
+
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 2
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x20
+
+config CONSOLE_SERIAL_UART_ADDRESS
+ hex
+ depends on DRIVERS_UART
+ default 0xFF690000
+
+config PMIC_BUS
+ int
+ default 0
+
+endif # BOARD_GOOGLE_VEYRON