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authorZhengShunQian <zhengsq@rock-chips.com>2016-10-28 16:16:04 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-11-03 13:53:56 +0100
commitf4401eb997dab0690261e0e42eab52131815d949 (patch)
treef47eb865d477fd8310fced2560a2d8cb1db79a5e /src/mainboard/google/veyron
parent8859afdb44194cacf0bc1c694b09eb94d568dab9 (diff)
downloadcoreboot-f4401eb997dab0690261e0e42eab52131815d949.tar.xz
google/veyron*: change .ddrconfig from 14 to 3
There are two configs, sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14. Changing .ddrconfig from 14 to 3 improves performance especially on contiguous memory accesses. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits .ddrconfig = 3 has multiple banks switching which improves DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/404691 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/veyron')
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc2
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
index 00dc549161..1c35c90047 100644
--- a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
@@ -69,7 +69,7 @@
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
- .ddrconfig = 14,
+ .ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
index a4bfb01ab7..c4ce972bd0 100644
--- a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
@@ -69,7 +69,7 @@
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
- .ddrconfig = 14,
+ .ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,