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| author | David Hendricks <dhendrix@chromium.org> | 2014-12-19 15:34:08 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-15 16:42:18 +0200 |
| commit | 16e32ed2f317c410382ed3c4a37380d4e82cf9bb (patch) | |
| tree | a7f9f78db47d180457f520f91f831f179b4341a8 /src/mainboard/google/veyron_brain/Kconfig | |
| parent | 7f00962e70c57b0fc6faf50b8fbf26f95b96e6d2 (diff) | |
| download | coreboot-16e32ed2f317c410382ed3c4a37380d4e82cf9bb.tar.xz | |
Brain: Initial mainboard import
This adds a directory with files copied over from Jerry, in addition to
build system related changes (configs/* and Kconfig stuff) necessary
to emerge-veyron_brain coreboot.
The next patch will account for differences between Jerry and Brain.
BUG=none
BRANCH=none
TEST=emerge-veyron_brain coreboot works
Change-Id: Ib0da9caf80f46991b96bcb5756f807237f0902e1
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 9509d6277dae25a78062c1301054a39f704b33fe
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I972f2623d9b0a43e3ea5312b3c4cd34ab44edc36
Original-Reviewed-on: https://chromium-review.googlesource.com/236989
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9637
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/google/veyron_brain/Kconfig')
| -rw-r--r-- | src/mainboard/google/veyron_brain/Kconfig | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig new file mode 100644 index 0000000000..1ec1d56ad4 --- /dev/null +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_VEYRON_BRAIN + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ID_SUPPORT + select BOARD_ROMSIZE_KB_4096 + select COMMON_CBFS_SPI_WRAPPER + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select EC_SOFTWARE_SYNC + select RAM_CODE_SUPPORT + select SOC_ROCKCHIP_RK3288 + select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_BOOTBLOCK_INIT + select HAVE_HARD_RESET + select RETURN_FROM_VERSTAGE + select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND + select VIRTUAL_DEV_SWITCH + +config MAINBOARD_DIR + string + default google/veyron_brain + +config MAINBOARD_PART_NUMBER + string + default "Veyron_Jerry" + +config MAINBOARD_VENDOR + string + default "Google" + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0 + +config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US + int + default 100 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +config BOOT_MEDIA_SPI_BUS + int + default 2 + +config DRAM_SIZE_MB + int + default 2048 + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0xFF690000 + +endif # BOARD_GOOGLE_VEYRON_BRAIN |