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author | Patrick Georgi <pgeorgi@chromium.org> | 2015-06-25 17:04:31 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-26 23:30:39 +0200 |
commit | bfa51979dcd923546f9dff0303d39f360ebd26b3 (patch) | |
tree | 0775a30958bc958fe1ea05434ea90a1abe89d633 /src/mainboard/google/veyron_danger/romstage.c | |
parent | 463d665cb13620b3700b61b5ffaaad7ef8ac0756 (diff) | |
download | coreboot-bfa51979dcd923546f9dff0303d39f360ebd26b3.tar.xz |
rockchip/rk3288: complete vboot configuration and move to SoC
Where vboot verification can start, and how the code flow looks like is more a
property of the SoC (and its properties, like amount of SRAM) rather than the
board.
Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10662
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_danger/romstage.c')
0 files changed, 0 insertions, 0 deletions