google/veyron_emile: Add new board of veyron

This is a copy of mickey and renamed.

CQ-DEPEND=CL:306967
BUG=chrome-os-partner:46658
TEST=build coreboot
BRANCH=veyron

Change-Id: I9e1232f3f1334ec747a5beb52f214635a7ab08ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9316a9ec27d5799e290add1e5818f4449b680fde
Original-Change-Id: I906de7bbc8b8e110e0774c14ec636a327230b325
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307620
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 49 insertions, 0 deletions

diff --git a/src/mainboard/google/veyron_emile/boardid.c b/src/mainboard/google/veyron_emile/boardid.c
new file mode 100644
index 0000000000..f7cddcc4fe
--- /dev/null
+++ b/src/mainboard/google/veyron_emile/boardid.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <stdlib.h>
+
+uint8_t board_id(void)
+{
+	static int id = -1;
+	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
+		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
+
+	if (id < 0) {
+		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
+		printk(BIOS_SPEW, "Board ID: %d.\n", id);
+	}
+
+	return id;
+}
+
+uint32_t ram_code(void)
+{
+	uint32_t code;
+	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
+		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
+
+	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
+	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
+
+	return code;
+}