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authorAaron Durbin <adurbin@chromium.org>2016-08-11 14:40:09 -0500
committerMartin Roth <martinroth@google.com>2016-08-18 22:04:34 +0200
commit08e842c0d10c69b8fc07f6b00ea4dbeb85ac6e58 (patch)
tree862eae8b485ccb5c72fadeb422ac98df26ecb3bf /src/mainboard/google/veyron_emile
parent240853bf25cbff39f0099dd6ed3fe0bfa75c9d0c (diff)
downloadcoreboot-08e842c0d10c69b8fc07f6b00ea4dbeb85ac6e58.tar.xz
Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/veyron_emile')
-rw-r--r--src/mainboard/google/veyron_emile/Kconfig2
-rw-r--r--src/mainboard/google/veyron_emile/bootblock.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/veyron_emile/Kconfig b/src/mainboard/google/veyron_emile/Kconfig
index 059dd1f147..d5884f9869 100644
--- a/src/mainboard/google/veyron_emile/Kconfig
+++ b/src/mainboard/google/veyron_emile/Kconfig
@@ -47,7 +47,7 @@ config MAINBOARD_VENDOR
string
default "Google"
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
int
default 2
diff --git a/src/mainboard/google/veyron_emile/bootblock.c b/src/mainboard/google/veyron_emile/bootblock.c
index 2fe913e067..726127564c 100644
--- a/src/mainboard/google/veyron_emile/bootblock.c
+++ b/src/mainboard/google/veyron_emile/bootblock.c
@@ -66,7 +66,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+ rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
setup_chromeos_gpios();
}