diff options
| author | jinkun.hong <jinkun.hong@rock-chips.com> | 2014-09-25 20:27:26 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-02 21:16:55 +0200 |
| commit | 3e9ea16c54dfe9ac593f772e5ba2f020b2e27c99 (patch) | |
| tree | d3b6dd0d236407be927ce20d8550fa4ea121b88b /src/mainboard/google/veyron_pinky | |
| parent | bfdd732b80a56e31d3bbe59de76a6a91b0f5b9e4 (diff) | |
| download | coreboot-3e9ea16c54dfe9ac593f772e5ba2f020b2e27c99.tar.xz | |
coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz
Add ddr3-samsung-2GB config and modify 533mhz linit.
Support ddr3 freq up to 800mhz.
Enable ODT at LPDDR3.
BUG=None
TEST=Boot Veyron Pinky
Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220113
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d
(cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9239
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/veyron_pinky')
| -rw-r--r-- | src/mainboard/google/veyron_pinky/sdram_configs.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 |
2 files changed, 79 insertions, 1 deletions
diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c index 21a483ce73..cc29de08d2 100644 --- a/src/mainboard/google/veyron_pinky/sdram_configs.c +++ b/src/mainboard/google/veyron_pinky/sdram_configs.c @@ -28,7 +28,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */ diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc new file mode 100644 index 0000000000..3fdbecf6a8 --- /dev/null +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two Samsung K4B4G1646D-BYK0 chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666000000, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, |