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| author | Patrick Georgi <pgeorgi@chromium.org> | 2015-06-25 17:04:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-26 23:30:39 +0200 |
| commit | bfa51979dcd923546f9dff0303d39f360ebd26b3 (patch) | |
| tree | 0775a30958bc958fe1ea05434ea90a1abe89d633 /src/mainboard/google/veyron_rialto/Kconfig | |
| parent | 463d665cb13620b3700b61b5ffaaad7ef8ac0756 (diff) | |
| download | coreboot-bfa51979dcd923546f9dff0303d39f360ebd26b3.tar.xz | |
rockchip/rk3288: complete vboot configuration and move to SoC
Where vboot verification can start, and how the code flow looks like is more a
property of the SoC (and its properties, like amount of SRAM) rather than the
board.
Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10662
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_rialto/Kconfig')
| -rw-r--r-- | src/mainboard/google/veyron_rialto/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 09098c159a..30c54f6a30 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select RAM_CODE_SUPPORT - select RETURN_FROM_VERSTAGE select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE |