diff options
| author | Julius Werner <jwerner@chromium.org> | 2015-03-24 16:54:38 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-22 08:50:30 +0200 |
| commit | ee426cf54eea43b8fb5194abe948f8e00d4f4b4c (patch) | |
| tree | 47b8926dad32b18a4064e43d2dc21cde846d7708 /src/mainboard/google/veyron_rialto | |
| parent | 2fdc61af6eea14450054cb0135bb6ad3f6a14831 (diff) | |
| download | coreboot-ee426cf54eea43b8fb5194abe948f8e00d4f4b4c.tar.xz | |
google/veyron_*: Increase SPI flash frequency to 24.75MHz
This patch increases the SPI clock for the ROM to 24.75MHz on all rk3288
(veyron) boards. This increases flash read speeds (and thereby decreases
boot time) significantly, but we don't seem to get any more increases by
going even higher. We have also seen occasional read failures at higher
speeds in certain configurations, so this frequency seems to be the best
option.
BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted on Jerry with Servo attached.
Change-Id: I9bdb62eff169fe2be33558caafe9891668589372
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a1d07da4266f2922b076dfae8396c24c6a84252b
Original-Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262645
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_rialto')
| -rw-r--r-- | src/mainboard/google/veyron_rialto/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index f59f8e941d..b47e2e2db6 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); setup_chromeos_gpios(); } |