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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-03-24 11:07:51 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-22 08:49:35 +0200 |
| commit | 37b7a666a2c010319d3400380880d28fc53bfed5 (patch) | |
| tree | ed646de58ef8240745bf69ba4e23275dbea8df8c /src/mainboard/google/veyron_rialto | |
| parent | 235f92203bdcac093c77b24f4c5489a9e48a2e48 (diff) | |
| download | coreboot-37b7a666a2c010319d3400380880d28fc53bfed5.tar.xz | |
chromeec: Support accessing memmap data over port 62/66
Some platforms cannot access the 900h-9ffh region over the LPC bus, so
it's necessary to access memmap data over the ACPI cmd / data ports.
BUG=chrome-os-partner:38224
TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify
system boots cleanly and battery status is updated immediately on plug /
unplug.
BRANCH=None
Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d
Original-Reviewed-on: https://chromium-review.googlesource.com/262314
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/9886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_rialto')
0 files changed, 0 insertions, 0 deletions