summaryrefslogtreecommitdiff
path: root/src/mainboard/google/veyron_speedy
diff options
context:
space:
mode:
authorJulius Werner <jwerner@chromium.org>2015-04-24 17:30:36 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-05-05 09:56:32 +0200
commit9ac9ac6309ecd937dedc2b857846158a728aca99 (patch)
tree0d72971d5dcd10965cd3515b7955115bc028bcd4 /src/mainboard/google/veyron_speedy
parent8ccdeaeb207031eea3881511acfaf3e949678f74 (diff)
downloadcoreboot-9ac9ac6309ecd937dedc2b857846158a728aca99.tar.xz
veyron: Initialize EC interrupt GPIO and add them to coreboot tables
This patch initializes the GPIO for the Chrome EC interrupt line on Veyron boards and passes its description through the coreboot table, so that payloads with keyboard support can use it to detect pending key presses. BRANCH=none BUG=chrome-os-partner:39514 TEST=Booted Jerry, confirmed that it could still detect keypresses. Confirmed that EC log does not show a huge amount of MKBP polls. Change-Id: I4de35ef411c3acc02282ebf8e764785a1e7bf6f1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ad95d667ef3af3fb217e3c370468dc1d6ec36c9 Original-Change-Id: I8b426621af088460929cfff0a4b46618e2a86725 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/267344 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/10088 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/google/veyron_speedy')
-rw-r--r--src/mainboard/google/veyron_speedy/chromeos.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron_speedy/chromeos.c b/src/mainboard/google/veyron_speedy/chromeos.c
index d509a01653..e0f816cdc1 100644
--- a/src/mainboard/google/veyron_speedy/chromeos.c
+++ b/src/mainboard/google/veyron_speedy/chromeos.c
@@ -32,6 +32,7 @@
#define GPIO_POWER GPIO(0, A, 5)
#define GPIO_RECOVERY GPIO(0, B, 1)
#define GPIO_ECINRW GPIO(0, A, 7)
+#define GPIO_ECIRQ GPIO(7, A, 7)
void setup_chromeos_gpios(void)
{
@@ -39,6 +40,7 @@ void setup_chromeos_gpios(void)
gpio_input_pullup(GPIO_LID);
gpio_input(GPIO_POWER);
gpio_input_pullup(GPIO_RECOVERY);
+ gpio_input(GPIO_ECIRQ);
}
void fill_lb_gpios(struct lb_gpios *gpios)
@@ -92,6 +94,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
GPIO_MAX_NAME_LENGTH);
count++;
+ /* EC interrupt: GPIO active high */
+ gpios->gpios[count].port = GPIO_ECIRQ.raw;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "EC interrupt",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
/* Reset: GPIO active high (output) */
gpios->gpios[count].port = GPIO_RESET.raw;
gpios->gpios[count].polarity = ACTIVE_HIGH;