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authorDavid Hendricks <dhendrix@chromium.org>2015-06-29 14:27:23 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-07-06 09:40:23 +0200
commite6883a3d9b198ccc9a2fc6d724f41e689aa6d1d6 (patch)
tree6d3a6f250fd88008d901aa8a1e01e3b7d1c6b96a /src/mainboard/google/veyron_speedy
parentaf42f069ea1bd8651a3e830323da27aee54290e5 (diff)
downloadcoreboot-e6883a3d9b198ccc9a2fc6d724f41e689aa6d1d6.tar.xz
veyron_*: Set vop_mode in devicetree.cb files
This avoids any ambiguity or breakage in case the vop_modes get shuffled around or changed in some future patch or copy+paste job. Brain and Rialto need some more work done so their devicetree.cb files will be updated in follow-up patches. BUG=none BRANCH=none TEST=compiled only (for danger, jerry, mickey, romy, speedy) Change-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db Original-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282610 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10776 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_speedy')
-rw-r--r--src/mainboard/google/veyron_speedy/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron_speedy/devicetree.cb b/src/mainboard/google/veyron_speedy/devicetree.cb
index 4c2ea8f709..b958e267d4 100644
--- a/src/mainboard/google/veyron_speedy/devicetree.cb
+++ b/src/mainboard/google/veyron_speedy/devicetree.cb
@@ -21,5 +21,6 @@
chip soc/rockchip/rk3288
device cpu_cluster 0 on end
register "vop_id" = "1"
+ register "vop_mode" = "VOP_MODE_EDP"
register "framebuffer_bits_per_pixel" = "16"
end