diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2020-08-05 14:50:40 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2020-08-06 17:42:31 +0000 |
| commit | ce25b947e0dbecf38b51789b5a54e09fe5f77a78 (patch) | |
| tree | 7758acec1ea3f9d29260d417030791f8a702306b /src/mainboard/google/volteer/romstage.c | |
| parent | 0cc63ccaa26c21d02025f3b1c31f2fc4e8adc697 (diff) | |
| download | coreboot-ce25b947e0dbecf38b51789b5a54e09fe5f77a78.tar.xz | |
mb/google/volteer: add support for ddr4 memory
Add new ddr_memory_cfg structure to support both DDR4 and LPDDR4x
memory types.
Change existing variant code to use the new meminit_ddr() call
instead of calling meminit_lpddr4x() directly.
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that
volteer still boots. NOTE that this only tests the lpddr4 side
of the implementation as I do not have a DDR4 board to test this on.
Change-Id: Id4bca2bfa97530f0d04a0e8d90f01b8281d2aea6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/romstage.c')
| -rw-r--r-- | src/mainboard/google/volteer/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 10c424ee4e..8893785774 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -15,7 +15,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct ddr_memory_cfg *board_cfg = variant_memory_params(); const struct spd_info spd_info = { .topology = MEMORY_DOWN, .md_spd_loc = SPD_CBFS, @@ -27,7 +27,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) mem_cfg->PchHdaEnable = 0; - meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); + meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); } bool mainboard_get_dram_part_num(const char **part_num, size_t *len) |