diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-23 10:13:10 +0530 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2020-04-01 19:12:30 +0000 |
commit | 555c9b6268febf001e887fbb9e3c3f0901a371ac (patch) | |
tree | d3b1968356086c05ac0894115f45b06cb8437e85 /src/mainboard/google/volteer/romstage.c | |
parent | a23e0c9d74b7f06738ebf28b068e1bd63f246982 (diff) | |
download | coreboot-555c9b6268febf001e887fbb9e3c3f0901a371ac.tar.xz |
soc/intel/tigerlake: Remove Jasper Lake SoC references
This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.
BUG=b:150217037
TEST=build tglrvp and volteer
Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/volteer/romstage.c')
-rw-r--r-- | src/mainboard/google/volteer/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 5d588b2d1d..46c5fecd1e 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -8,7 +8,7 @@ #include <baseboard/variants.h> #include <gpio.h> #include <soc/gpio.h> -#include <soc/meminit_tgl.h> +#include <soc/meminit.h> #include <soc/romstage.h> #include <variant/gpio.h> |