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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-04-21 17:07:57 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-04-30 16:35:53 +0000 |
| commit | b8bfe142c6bbaf3674e9d0ff70b42ca32bcb4df4 (patch) | |
| tree | 27f20cedc1f7f4de99b583576f8dce243c6645e0 /src/mainboard/google/volteer/variants/baseboard/devicetree.cb | |
| parent | 4cea00a64f6e2080556a63863d1b792654c01cd8 (diff) | |
| download | coreboot-b8bfe142c6bbaf3674e9d0ff70b42ca32bcb4df4.tar.xz | |
mb/google/voteer: Enable DevSlp for SATA port1
BUG=b:152893285
BRANCH=none
TEST=Build and boot to OS volteer with Intel SATA and reboot
from OS console
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 12ae87afcd..b68966331c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -77,6 +77,7 @@ chip soc/intel/tigerlake register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, |