soc/intel/tigerlake: Reorganize memory initialization support

This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.

1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.

TEST=Verified that volteer still boots and memory initialization is
successful.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
index d5bc63a08c..a7169fe8c9 100644
--- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
@@ -23,7 +23,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num);
 
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 
-const struct mb_lpddr4x_cfg *variant_memory_params(void);
+const struct lpddr4x_cfg *variant_memory_params(void);
 int variant_memory_sku(void);
 
 #endif /* __BASEBOARD_VARIANTS_H__ */