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author | Furquan Shaikh <furquan@google.com> | 2020-03-26 15:36:19 -0700 |
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committer | Furquan Shaikh <furquan@google.com> | 2020-04-02 16:53:55 +0000 |
commit | 5b1f335ef8aed95e01f040bc7074fb00acc8ab7e (patch) | |
tree | a119e13f3d7a88955dee92a9de23ab6973f5673e /src/mainboard/google/volteer/variants/baseboard/memory.c | |
parent | 3c57819005af59064ea0397e8b1ed59fab5a8f7c (diff) | |
download | coreboot-5b1f335ef8aed95e01f040bc7074fb00acc8ab7e.tar.xz |
soc/intel/tigerlake: Reorganize memory initialization support
This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.
1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.
TEST=Verified that volteer still boots and memory initialization is
successful.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants/baseboard/memory.c')
-rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/memory.c | 65 |
1 files changed, 43 insertions, 22 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index db2946dd33..f2c5a5a146 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -9,38 +9,59 @@ #include <baseboard/variants.h> #include <gpio.h> -static const struct mb_lpddr4x_cfg baseboard_memcfg = { - /* DQ byte map */ +static const struct lpddr4x_cfg baseboard_memcfg = { + /* DQ CPU<>DRAM map */ .dq_map = { - { 0, 1, 2, 3, 4, 5, 6, 7, /* Byte 0 */ - 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ - { 7, 2, 6, 3, 5, 1, 4, 0, /* Byte 2 */ - 10, 8, 9, 11, 15, 12, 14, 13 }, /* Byte 3 */ - { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 4 */ - 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 5 */ - { 7, 0, 1, 6, 5, 4, 2, 3, /* Byte 6 */ - 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */ - { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 0 */ - 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ - { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */ - 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */ - { 3, 2, 1, 0, 7, 4, 5, 6, /* Byte 4 */ - 15, 14, 13, 12, 8, 9, 10, 11 }, /* Byte 5 */ - { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */ - 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */ + [0] = { + { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ + }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ }, .ect = 0, /* Disable Early Command Training */ }; -const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +const struct lpddr4x_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } |