diff options
author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-09-23 16:37:21 +0530 |
---|---|---|
committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-09-25 16:45:07 +0000 |
commit | e60155ff13fb61c20e01601e6a58ff1fe5509b8b (patch) | |
tree | bdc1b58dbbdcafbc910533d032e8b1d3aad3902a /src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h | |
parent | fb2f356d89de19994214dbe01ef7c02e02f24be0 (diff) | |
download | coreboot-e60155ff13fb61c20e01601e6a58ff1fe5509b8b.tar.xz |
volteer: Create boldar variant
Create the boldar variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
Add "memory/Makefile.inc" generated by gen_part_id.go
BUG=b:162202257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_BOLDAR
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I92b4b917448d8e5e9176cb983adf7b209956d2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h')
-rw-r--r-- | src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif |