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author | nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> | 2020-08-20 16:43:55 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-09 13:37:41 +0000 |
commit | 44097e21cc3dcb81690de68bbcda2b194ac427fe (patch) | |
tree | 7f860c49f25cfc642479dbf3c84f7071180a2fce /src/mainboard/google/volteer/variants/eldrid/memory.c | |
parent | 404a42bb3a7688274a3127f1b3873eee5a8808ad (diff) | |
download | coreboot-44097e21cc3dcb81690de68bbcda2b194ac427fe.tar.xz |
mb/google/volteer/variants/eldrid: add memory.c for ddr4 support
Add new memory.c to support DDR4 memory types.
Use the new meminit_ddr() and variant_memory_sku() for eldrid variant
code on memory.c
The initial settings override the baseboard from volteer and fine tune
gpio.c and overridetree.cb on eldrid's configuration.
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid
can boots. NOTE that tests the ddr4 side of the implementation.
Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/eldrid/memory.c')
-rw-r--r-- | src/mainboard/google/volteer/variants/eldrid/memory.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/eldrid/memory.c b/src/mainboard/google/volteer/variants/eldrid/memory.c new file mode 100644 index 0000000000..577734dbcf --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ +static const struct mb_ddr4_cfg eldrid_memcfg = { +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_DDR4, + .ddr4_cfg = &eldrid_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_0, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} |