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| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-06-30 14:18:41 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-30 18:08:31 +0000 |
| commit | 9f9b97e6bc57a9a80c6f75046a3987b223433e10 (patch) | |
| tree | 642992d1c9d823e06f435aef1481731f7d1c6f72 /src/mainboard/google/volteer | |
| parent | 6caa4769c763b10a440637ce9c8d11ef1764c90d (diff) | |
| download | coreboot-9f9b97e6bc57a9a80c6f75046a3987b223433e10.tar.xz | |
mb/google/volteer: set tcc_offset value to 10
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value
Change-Id: I6438547e09a3ff3a1c01addfcc01383e89f5b435
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/volteer')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 0c581a51f2..300fb7e729 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -222,6 +222,8 @@ chip soc/intel/tigerlake register "Device4Enable" = "1" + register "tcc_offset" = "10" # TCC of 90 + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |