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| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2020-06-12 02:59:26 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-06-25 20:58:55 +0000 |
| commit | 154625bcb2cac1f120a9d0c03da00f2e8c524273 (patch) | |
| tree | 751c2ce26be424d07a056f0067268a67eb6d3ec1 /src/mainboard/google/volteer | |
| parent | bc6aa222a61152e4eb37f836a52aaa74bcdfed63 (diff) | |
| download | coreboot-154625bcb2cac1f120a9d0c03da00f2e8c524273.tar.xz | |
mb/google/volteer: Enable HECI interface
This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
BUG=b:159615125
TEST=Build and boot volteer. Run lspci and check pcie device
00:16.0 Communication controller: Intel Corporation Device a0e0
Change-Id: I68eb51c6a0af77982c060767993265764a2bc926
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 705da1d0f4..0c581a51f2 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -43,6 +43,9 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # Enable heci communication + register "HeciEnabled" = "1" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "0" |