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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2020-06-10 20:16:07 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-06-14 16:51:47 +0000
commit83ca56acdfc7a98945f673c7739764ef25b967f2 (patch)
tree0c215b158dfd67b571a6dde1af2adb8a0522e230 /src/mainboard/google/volteer
parent7454005a4fd611cc2ad4b490442834e50272fd1b (diff)
downloadcoreboot-83ca56acdfc7a98945f673c7739764ef25b967f2.tar.xz
mb/google/volteer/var/terrador: Update dq/dqs mappings
Update dq/dqs mappings based on terrador schematics. BUG=b:156435028,b:151978872 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I97697a3dd9b88eaffe6e2b1be7bd346979cbc956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/volteer')
-rw-r--r--src/mainboard/google/volteer/variants/terrador/Makefile.inc2
-rw-r--r--src/mainboard/google/volteer/variants/terrador/memory.c60
2 files changed, 62 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/terrador/Makefile.inc b/src/mainboard/google/volteer/variants/terrador/Makefile.inc
index c9a128d72a..3a7557b548 100644
--- a/src/mainboard/google/volteer/variants/terrador/Makefile.inc
+++ b/src/mainboard/google/volteer/variants/terrador/Makefile.inc
@@ -4,4 +4,6 @@ SPD_SOURCES =
bootblock-y += gpio.c
+romstage-y += memory.c
+
ramstage-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c
new file mode 100644
index 0000000000..773e88561d
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/terrador/memory.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+
+static const struct lpddr4x_cfg terrador_memcfg = {
+ /* DQ byte map */
+ .dq_map = {
+ [0] = {
+ { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */
+ { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */
+ },
+ [1] = {
+ { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */
+ { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */
+ },
+ [2] = {
+ { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */
+ { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */
+ },
+ [3] = {
+ { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */
+ { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */
+ },
+ [4] = {
+ { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */
+ { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */
+ },
+ [5] = {
+ { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */
+ { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */
+ },
+ [6] = {
+ { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */
+ { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */
+ },
+ [7] = {
+ { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */
+ { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */
+ },
+ },
+
+ /* DQS CPU<>DRAM map */
+ .dqs_map = {
+ [0] = { 0, 1 }, /* DDR0_DQS[1:0] */
+ [1] = { 0, 1 }, /* DDR1_DQS[1:0] */
+ [2] = { 1, 0 }, /* DDR2_DQS[1:0] */
+ [3] = { 1, 0 }, /* DDR3_DQS[1:0] */
+ [4] = { 0, 1 }, /* DDR4_DQS[1:0] */
+ [5] = { 0, 1 }, /* DDR5_DQS[1:0] */
+ [6] = { 1, 0 }, /* DDR6_DQS[1:0] */
+ [7] = { 1, 0 }, /* DDR7_DQS[1:0] */
+ },
+
+ .ect = 1, /* Enable Early Command Training */
+};
+
+const struct lpddr4x_cfg *variant_memory_params(void)
+{
+ return &terrador_memcfg;
+}