diff options
author | Paul Fagerburg <pfagerburg@chromium.org> | 2020-08-07 02:45:37 +0000 |
---|---|---|
committer | Paul Fagerburg <pfagerburg@chromium.org> | 2020-08-07 03:16:46 +0000 |
commit | ad3dceae303cacee3e836e918a26380c9bfe94a2 (patch) | |
tree | 6a326393df6231176540bdbd257456122d194528 /src/mainboard/google/volteer | |
parent | 19895f80138e47fa0e89aeb32e31801cdfb343ff (diff) | |
download | coreboot-ad3dceae303cacee3e836e918a26380c9bfe94a2.tar.xz |
Revert "mb/google/volteer/var/halvor: Update dq/dqs mappings"
This reverts commit 3d813cbede650a89a519d5896652328e4ecf88c6.
Reason for revert: the CL made the build unstable.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I9d067eb13196ff7d537d557d8ff864b1572a3b04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43076
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer')
-rw-r--r-- | src/mainboard/google/volteer/variants/halvor/Makefile.inc | 2 | ||||
-rw-r--r-- | src/mainboard/google/volteer/variants/halvor/memory.c | 60 |
2 files changed, 0 insertions, 62 deletions
diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 343c7dbb95..13269db5ec 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -romstage-y += memory.c - bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c deleted file mode 100644 index 754c7a00c5..0000000000 --- a/src/mainboard/google/volteer/variants/halvor/memory.c +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> - -static const struct lpddr4x_cfg halvor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 12, 13, 9, 11, 8, 15, 14, }, /* DDR0_DQ0[7:0] */ - { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ - { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ - { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ - { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ - { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - - .ect = 1, /* Enable Early Command Training */ -}; - -const struct lpddr4x_cfg *variant_memory_params(void) -{ - return &halvor_memcfg; -} |