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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-07-15 10:52:42 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-07-18 16:04:31 +0000
commit6d391e649f8a32613d489e513eb00c05d07a7147 (patch)
treefff5b113ac272ebc9adfc3df40c168aad786f0f0 /src/mainboard/google/volteer
parentff75c21e6d6c84d4d78529afc1b145104631eaa9 (diff)
downloadcoreboot-6d391e649f8a32613d489e513eb00c05d07a7147.tar.xz
mb/google/volteer: Update DPTF with temp sensor 3
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. Also missed a swap in the passive policies of TSR0 and TSR1. This patch fixes those. BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index f0bb25bfeb..e0d3beaaa2 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -311,18 +311,26 @@ chip soc/intel/tigerlake
TEMP_PCT(45, 56),
TEMP_PCT(42, 46),
TEMP_PCT(39, 36),}}"
+ register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3,
+ .thresholds={TEMP_PCT(50, 90),
+ TEMP_PCT(47, 69),
+ TEMP_PCT(45, 56),
+ TEMP_PCT(42, 46),
+ TEMP_PCT(39, 36),}}"
## Passive Policy
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
- register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
- register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 6000)"
+ register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000)"
+ register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000)"
register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000)"
+ register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)"
## Critical Policy
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)"
register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)"
register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)"
+ register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)"
## Power Limits Control
# 10-15W PL1 in 200mW increments, avg over 28-32s interval