diff options
| author | Duncan Laurie <dlaurie@google.com> | 2018-11-08 15:46:16 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-11-13 16:32:27 +0000 |
| commit | 98456f4ee6e1d7df2863e2fafe8e505522a48da8 (patch) | |
| tree | 3631482088033a55286946fa7cbbb17d4479b50f /src/mainboard/google/zoombini | |
| parent | 6efa5c38460b28d650231429ae4fc9a0be7fddba (diff) | |
| download | coreboot-98456f4ee6e1d7df2863e2fafe8e505522a48da8.tar.xz | |
mb/cannonlake: Remove SmbusEnable from devicetree
Remove the SmbusEnable parameter from all Cannon Lake mainboards.
Instead this will be determined by the enable state of the SMBUS
PCI device.
Change-Id: I7ece6768da4c517747af12a07012583575816ae1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/zoombini')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/baseboard/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index c7ef264eaa..36c6595feb 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" # Intel Common SoC Config diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index c3a546ec2d..b014353e0b 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -29,7 +29,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" # Intel Common SoC Config |