diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-01-25 17:39:06 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-01 16:09:53 +0000 |
| commit | e85e0f57acf1b1dfe86b54689cf89659bfd94a54 (patch) | |
| tree | 058dcda20d4850a047d53b20d7406855363c9229 /src/mainboard/google/zoombini | |
| parent | 3dd88f175d1863534a8bdb5c19d718becc31e6f3 (diff) | |
| download | coreboot-e85e0f57acf1b1dfe86b54689cf89659bfd94a54.tar.xz | |
mainboard/google/meowth: Turn on DBC over USB3.0
Intel DCI (direct connect interface) allows debug Intel target using
USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0
only.
BUG=None
TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot
image. Using DAL to halt/run CPU.
Change-Id: I39e68dabfcb9e659733019334299e562eee3681d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google/zoombini')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 20654e39d8..c0e4ac3317 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -6,6 +6,9 @@ chip soc/intel/cannonlake register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" + # Debug Option, set to DBC over USB 3.0 port only + register "DebugConsent" = "DebugConsent_USB3_DBC" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE |