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authorNick Vaccaro <nvaccaro@chromium.org>2017-12-02 10:26:31 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2018-01-11 01:07:35 +0000
commit8508f7d18286ca9207151951e28578d461cc799d (patch)
treeecf85b901e6478f3a8dc4f0d1042055128610b5b /src/mainboard/google/zoombini
parentffe6dd1f43d6fb2eefd79b2346c4eec6e477d74c (diff)
downloadcoreboot-8508f7d18286ca9207151951e28578d461cc799d.tar.xz
mainboard/google/zoombini: enable USB and assign acpi irq
-add USB2 and USB3 to devicetree -add TPM_TIS_ACPI_INTERRUPT to Kconfig -map gpe0_dw0, gpe0_dw1, and gpe0_dw2 blocks BUG=b:64395641 BRANCH=chromeos-2016.05 TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ia7ed76591d9d8d94bbf5652313c478495ce005fa Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/zoombini')
-rw-r--r--src/mainboard/google/zoombini/Kconfig4
-rw-r--r--src/mainboard/google/zoombini/variants/baseboard/devicetree.cb41
2 files changed, 45 insertions, 0 deletions
diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig
index 2fe8fec04f..8e1cfbbcbe 100644
--- a/src/mainboard/google/zoombini/Kconfig
+++ b/src/mainboard/google/zoombini/Kconfig
@@ -86,4 +86,8 @@ config ZOOMBINI_USE_SPI_TPM
select SPI_TPM
select TPM2
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 76 # GPE0_DW2_12 (GPP_C12)
+
endif # BOARD_GOOGLE_BASEBOARD_ZOOMBINI
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
index 771bab2af1..1bf5dba562 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
@@ -1,9 +1,50 @@
chip soc/intel/cannonlake
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "PMC_GPP_A"
+ register "gpe0_dw1" = "PMC_GPP_B"
+ register "gpe0_dw2" = "PMC_GPP_C"
+
device cpu_cluster 0 on
device lapic 0 on end
end
+ # FSP configuration
+ register "SaGv" = "3"
+ register "FspSkipMpInit" = "1"
+ register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "1"
+
+ # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
+ # communication before memory is up.
+ register "gspi[0]" = "{
+ .speed_mhz = 1,
+ .early_init = 1,
+ }"
+
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"
+ register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+ register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+ register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+ register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+ register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+ register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+ register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device