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authorLijian Zhao <lijian.zhao@intel.com>2018-08-20 14:06:13 -0700
committerMartin Roth <martinroth@google.com>2018-08-28 15:15:26 +0000
commit903c9764a16fba61bf90187d6f7e2afde37cfec0 (patch)
tree613569c7c546b90d941d55374b3f80fa59f30bf8 /src/mainboard/google/zoombini
parent5dff396befca2241f8323b422cbf6cc5b66a7488 (diff)
downloadcoreboot-903c9764a16fba61bf90187d6f7e2afde37cfec0.tar.xz
soc/intel/cannonlake: Change LPDDR4 to MEMCFG
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. Consider the case of reading SPD from SMBus other than providing SPD pointer directly. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28248 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zoombini')
-rw-r--r--src/mainboard/google/zoombini/Kconfig2
-rw-r--r--src/mainboard/google/zoombini/memory.c14
-rw-r--r--src/mainboard/google/zoombini/romstage.c4
-rw-r--r--src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h4
-rw-r--r--src/mainboard/google/zoombini/variants/meowth/memory.c14
5 files changed, 19 insertions, 19 deletions
diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig
index d28f6621a3..656d8b0b70 100644
--- a/src/mainboard/google/zoombini/Kconfig
+++ b/src/mainboard/google/zoombini/Kconfig
@@ -12,7 +12,7 @@ config BOARD_GOOGLE_BASEBOARD_ZOOMBINI
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CANNONLAKE
- select SOC_INTEL_CANNONLAKE_LPDDR4_INIT
+ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
if BOARD_GOOGLE_BASEBOARD_ZOOMBINI
diff --git a/src/mainboard/google/zoombini/memory.c b/src/mainboard/google/zoombini/memory.c
index e1f525590f..802467c44b 100644
--- a/src/mainboard/google/zoombini/memory.c
+++ b/src/mainboard/google/zoombini/memory.c
@@ -17,10 +17,10 @@
#include <baseboard/gpio.h>
#include <compiler.h>
#include <gpio.h>
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
-static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
- .dq_map[LP4_CH0] = {
+static const struct cnl_mb_cfg baseboard_lpddr4_cfg = {
+ .dq_map[DDR_CH0] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
@@ -37,7 +37,7 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
{ 0xFF, 0x00 },
},
- .dq_map[LP4_CH1] = {
+ .dq_map[DDR_CH1] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
@@ -61,8 +61,8 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
* the index = pin number on lpddr4 part
* the value = pin number on SoC
*/
- .dqs_map[LP4_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
- .dqs_map[LP4_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 },
+ .dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
+ .dqs_map[DDR_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 },
/* Baseboard uses three 100 Ohm rcomp resistors */
.rcomp_resistor = { 100, 100, 100 },
@@ -82,7 +82,7 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
.ect = 0,
};
-const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
+const struct cnl_mb_cfg *__weak variant_lpddr4_config(void)
{
return &baseboard_lpddr4_cfg;
}
diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c
index 8e191776d0..4bd0ede14f 100644
--- a/src/mainboard/google/zoombini/romstage.c
+++ b/src/mainboard/google/zoombini/romstage.c
@@ -14,7 +14,7 @@
*/
#include <baseboard/variants.h>
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
@@ -24,6 +24,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
.spd_spec.spd_index = variant_memory_sku(),
};
- cannonlake_lpddr4_init(&memupd->FspmConfig,
+ cannonlake_memcfg_init(&memupd->FspmConfig,
variant_lpddr4_config(), &spd);
}
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
index eab081da54..eac0feea6f 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
@@ -17,7 +17,7 @@
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
#include <soc/gpio.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -35,7 +35,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
/* Return LPDDR4 configuration structure. */
-const struct lpddr4_cfg *variant_lpddr4_config(void);
+const struct cnl_mb_cfg *variant_lpddr4_config(void);
/* Return memory SKU for the board. */
size_t variant_memory_sku(void);
diff --git a/src/mainboard/google/zoombini/variants/meowth/memory.c b/src/mainboard/google/zoombini/variants/meowth/memory.c
index c72ffeab4f..02c9ab9048 100644
--- a/src/mainboard/google/zoombini/variants/meowth/memory.c
+++ b/src/mainboard/google/zoombini/variants/meowth/memory.c
@@ -16,10 +16,10 @@
#include <baseboard/variants.h>
#include <baseboard/gpio.h>
#include <gpio.h>
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
-static const struct lpddr4_cfg meowth_lpddr4_cfg = {
- .dq_map[LP4_CH0] = {
+static const struct cnl_mb_cfg meowth_lpddr4_cfg = {
+ .dq_map[DDR_CH0] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
@@ -36,7 +36,7 @@ static const struct lpddr4_cfg meowth_lpddr4_cfg = {
{ 0xFF, 0x00 },
},
- .dq_map[LP4_CH1] = {
+ .dq_map[DDR_CH1] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
@@ -65,8 +65,8 @@ static const struct lpddr4_cfg meowth_lpddr4_cfg = {
* and it will translate that and display 8 values per channel.
* Those values are copied into the dqs_map arrays below.
*/
- .dqs_map[LP4_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
- .dqs_map[LP4_CH1] = { 2, 3, 1, 0, 7, 5, 6, 4 },
+ .dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
+ .dqs_map[DDR_CH1] = { 2, 3, 1, 0, 7, 5, 6, 4 },
/* Meowth uses three 100 Ohm rcomp resistors */
.rcomp_resistor = { 100, 100, 100 },
@@ -86,7 +86,7 @@ static const struct lpddr4_cfg meowth_lpddr4_cfg = {
.ect = 1,
};
-const struct lpddr4_cfg *variant_lpddr4_config(void)
+const struct cnl_mb_cfg *variant_lpddr4_config(void)
{
return &meowth_lpddr4_cfg;
}